ESD Table of Contents Embedded System Design: A Unified Hardware/Software Introduction Frank Vahid and Tony Givargis Table of Contents Preface 1.1. Embedded systems overview 1.2. Design challenge - optimizing design metrics 1.2.1. Common design metrics 1.2.2. The time-to-market design metric 1.2.3. The NRE and unit cost design metric 1.2.4. The performance design metric 1.3.
May 28, 2017 - Source: F. Givargis, Embedded System Design: A Unified Hardware Software Approach. Kris Kuchcinski (LTH). Low data-rate DSP. Slow control loops code generator. High level synth. User interface.
2 Embedded Systems Design: A Unified 5 Hardware/Software Introduction, (c) 2000 Vahid/Givargis Designer’s perspective • Two key tasks – Processing images and. Embedded Systems Design. 2000 Vahid/Givargis 5. Embedded Systems Design: A Unified Hardware/Software Introduction, (c).
Processor technology 1.3.1. General-purpose processors - software 1.3.2. Single-purpose processors - hardware 1.3.3. Application-specific processors 1.4. IC technology 1.4.1. Full-custom/VLSI 1.4.2.
Semi-custom ASIC (gate array and standard cell) 1.4.3. Design Technolgy 1.5.1. Compliation/Synthesis 1.5.2. Libraries/IP 1.5.3. Test/Verification 1.5.4. More productivity improvers 1.5.5.
Tradeoffs 1.6.1. Design productivity gap 1.7. Summary and book outline 1.8. References and further reading 1.9.
Exercises 2.1. Introduction 2.2.
Combinational Logic 2.2.1. Transistors and logic gates 2.2.2. Basic combinational logic design 2.2.3.
RT-level combinational components 2.3. Sequential logic 2.3.1. Flip-flops 2.3.2.
RT-level sequential components 2.3.3. Sequential logic design 2.4. Custom single-purpose processor design 2.5.
RT-level custom single-purpose processor design 2.6. Optimizing custom single-purpose processors 2.6.1.
Optimizing the original program 2.6.2. Optimizing the FSMD 2.6.3. Optimizing the datapath 2.6.4. Optimizing the FSM 2.7. References and further reading 2.9.
Exercises 3.1. Introduction 3.2. Basic architecture 3.2.1. Datapath 3.2.2. Control unit 3.2.3. Operation 3.3.1.
Instruction execution 3.3.2. Piplelining 3.3.3. Superscalar and VLIW architectures 3.4. Programmer's view 3.4.1.
Instruction set 3.4.2. Program and data memory space 3.4.3. Registers 3.4.4. Interrupts 3.4.6. Operating Systems 3.5.
Development environment 3.5.1. Design flow and tools 3.5.2.
Testing and debugging 3.6 Application-specific instruction-set processors (ASIP's) 3.6.1. Microcontrollers 3.6.2. Digital signal processors (DSP) 3.6.3. Less-general ASIP environments 3.7.
Selecting a microprocessor 3.8. General-purpose processor design 3.9. Summary 3.10. References and further reading 3.11. Exercises 4.1. Introduction 4.2.
Timers, counters, and watchdog timers 4.3. Pulse width modulator 4.5. LCD controller 4.6. Keypad controller 4.7. Stepper motor controller 4.8.
Analog-digital converters 4.9. Real-time clocks 4.10. Summary 4.11. References and further reading 4.12. Exercises 5.1. Introduction 5.2. Memory write ability and storage permanence 5.2.1 Write ability 5.2.2.
Storage permanence 5.2.3. Tradeoffs 5.3. Common memory types 5.3.1. Introduction to 'read-only' memories - ROM 5.3.2. Mask-programmed ROM 5.3.3.
OTP ROM - one-time programmable ROM 5.3.4. EPROM - erasable programmable ROM 5.3.5. EEPROM - electrically-erasable programmable ROM 5.3.6. Flash memory 5.3.7. Introduction to read-write memory - RAM 5.3.8. SRAM - Static RAM 5.3.9. DRAM - Dynamic RAM 5.3.10 PSRAM - Pseudo-static RAM 5.3.11.
NVRAM - Non-volatile RAM 5.4. Composing memories 5.5. Memory hierarchy and cache 5.5.1. Cache mapping techniques 5.5.2. Cache replacement policy 5.5.3.
Cache write techniques 5.5.4. Cache impact on system performance 5.6. Advanced RAM 5.6.1. The basic DRAM 5.6.2. Fast page mode (FPM DRAM) 5.6.3. Extended data out DRAM (EDO DRAM) 5.6.4.
Synchronous (S) and enhanced synchronous (ES) DRAM 5.6.5. Rambus DRAM (RDRAM) 5.6.6. DRAM integration problem 5.6.7. Memory management unit (MMU) 5.7.
References and further reading 5.9. Exercises 6.1. Introduction 6.2. Communication basics 6.2.1. Basic terminology 6.2.2.
Basic protocol concepts 6.3. Microprocessor interfacing: I/O addressing 6.3.1.
Port and bus-based I/O 6.3.2. Memory-mapped I/O and standard I/O 6.4. Microprocessor interfacing: interrupts 6.5. Microprocessor interfacing: Direct memory access 6.6. Arbitration 6.6.1.
Priority arbiter 6.6.2. Daisy-chain arbitration 6.6.3. Networked-oriented arbitration methods 6.7. Multi-level bus architectures 6.8. Advanced communication principles 6.8.1. Parallel communication 6.8.2.
Serial communication 6.8.3. Wireless communication 6.8.4. Layering 6.8.5. Error detection and correction 6.9.
Serial Protocols 6.9.1. I 2C bus 6.9.2. CAN bus 6.9.3. FireWire bus 6.9.4. Parallel protocols 6.10.1.
PCI bus 6.10.2. ARM bus 6.11. Wireless protocols 6.11.1. Bluetooth 6.11.2. IEEE 802.11 6.12.
Summary 6.13. References and further reading 6.14. Exercises 7.1. Introduction 7.2. Digital camera 7.2.1.
User's perspective 7.2.2. Designer's perspective 7.3. Specification 7.3.1. Informal functional specification 7.3.2. Non-functional specification 7.3.3. Executable specification 7.4.
Design 7.4.1. Implementation 1: 8051-based design 7.4.2. Implementation 2: fixed point FDCT 7.4.3.
Implementation 3: hardware FDCT 7.5. References and further reading 7.7. Exercises 8.1.
Introduction 8.2. Languages, text vs. Graphics 8.2.1. Languages 8.2.2.
Textual languages versus graphical languages 8.3. An introductory example 8.4. A basic state machine model: finite-state machines (FSM) 8.5. Finite-state machines with datapath model: FSMD 8.6.
Using state machines 8.6.1. Describing a system as a state machine 8.6.2. Comparing the state machine and sequential program models 8.6.3.
Capturing a state machine model in a sequential programming language 8.7. Hierarchial/Concurrent state machine model (HCFSM) and the Statecharts lanugage 8.8. Program-state machine model (PSM) 8.9. The role of an appropriate model and language 8.10. Concurrent process model 8.10. Concurrent processes 8.10.1.
Process create and terminate 8.10. Stylewriter 4 04 Keygen Software there. 2. Process suspend and resume 8.10.3.
Process join 8.12. Communication among processes 8.12.1. Shared memory 8.12.2. Message passing 8.13. Synchonization among processes 8.13.1.
Condition variables 8.13.2. Monitors 8.14. Implementation 8.14.1. Creating and terminating processes 8.14.2. Suspending and resuming processes 8.14.3. Joining a process 8.14.4.
Scheduling processes 8.15. Dataflow model 8.16. Real-time systems 8.16.1.
Windows CE 8.16.2. Summary 8.18. References and further reading 8.19. Exercises 9.1. Introduction 9.2. Open-loop and closed-loop control systems 9.2.1.
Overview 9.2.2. A first example: an open-looped automobile cruise-controller 9.2.3.
A second example: a closed-loop automobile cruise-controller 9.3. General control systems and PID controllers 9.3.1. Control objectives 9.3.2. Modeling real physical systems 9.3.3. Controller design 9.4. Fuzzy control 9.5.
Practial Issues Realted to Computer based Control 9.6. Benefits of Computer Based Control Implementations 9.7. References and further reading 9.9. Exercises 10.1. Introduction 10.2. Full-custom (VLSI) IC technology 10.3.
Semi-custom (ASIC) IC technology 10.3.1. Gate array semi-custom IC technology 10.3.2. Standard cell semi-custom IC technology 10.4. Programmable logic device (PLD) IC technology 10.5. Summary 10.6. References and further reading 10.7.
Exercises 11.1. Introduction 11.2. Automation: synthesis 11.2.1.
The parallel evolution of compilation and synthesis 11.2.2. Synthesis levels 11.2.3.
Logic synthesis 220.127.116.11. Two-level logic minimization 18.104.22.168. Multi-level logic minimization 22.214.171.124. FSM synthesis 126.96.36.199.
Technology mapping 188.8.131.52. The impact of complexity on logic synthesis users 184.108.40.206.
Integration logic synthesis and physical design 11.2.4. Register-transfer synthesis 11.2.5.
Behavioral synthesis 11.2.6. System synthesis and hardware/software codesign 11.2.7. Synthesis requires temporal rather than spatial thinking 11.3.
Verification: hardware/software co-simulation 11.3.1. Formal verification and simulation 11.3.2. Simulation speed 11.3.3. Hardware-software co-simulation 11.3.4. Emulators 11.4. Reuse: intellecutal property cores 11.4.1.
Hard, soft and firm cores 11.4.2. New challenges posed by cores to processor providers 11.4.2. New challenges posed by cores to processor users 11.5. Design process models 11.6. Summary 11.7.
References and further readings 11.8.
CPE 746: Real-Time Embedded Systems CPE 746: Real-time Embedded Systems Design Fall Term 2007 Jordan University of Science and Technology-JUST Announcements • Class room is: C2011• My office hours: Sun, Tue: 10:15-11:15, Thru: 10:15:1:15, Mon: 1:15-2:15. Or by appointment.• • with ModelSim.
Thanks to Abdelrahman Abu ELhaj• Download Miktex (PC version of Latex) from. And the text editor: Winedt form. Install Miktex first!• • • The Synthesizer• shows how to include.eps figure into your document.• The project details are posted on the web.
Please read it.• My office Hours: Sun, Tue:10:15-11:15, Mon: 1:15-2:15, and Thru:10:15-2:15pm or by appointment.• Today ensha'lah we will continue from were we stopped, and talk about the project.• There will be NO class today (Monday 8/10/2007). I will make it up for you later ensha'lah.• The presentations are uploaded now.• There will be NO class tomorrow (Monday ), last day of the year-have fun.• The final All the presentations are included in the final exam. It will be open notes as it was with the midterm. Grades Motivation and Objectives: Welcome to the Embedded System Design course.
This course covers the principles of real-time and embedded systems inherent in many hardware platforms and applications being developed for engineering and science as well as for ubiquitous systems, including robotics and manufacturing, interactive and multimedia, immersive and omnipresent applications. As part of this course, students will learn about real-time and quality of service system principles, understand real-time operating systems and the resource management and quality of service issues that arise, and construct sample applications on representative platforms. Homework Assignment Homework assignments can be submitted by e-mail to:, ( but hardcopies are also accepted). Please name your file as your last name followed by homework number, followed by course number (746), for example, tawalbeh-hw1-746.pdf. Also make sure that your name and number is printed within the homework file.
Design Project Click the link for the project Exams: • TBA Plan of the Course-Slides • Week 1: Introduction and general overview of the course.